Professional Experience
Image America
St. Louis, MO
Consulting Job
March 1999-April 1999

Performed a rescue operation on a digital camera design that had been delayed by 10 months at Boeing. I was hired by the contractor and got full functionality of the design in three weeks. Redesigned processing board and FPGAs used for frame buffering.

LSI Logic
Irvine, CA
Consumer Product Division
March 1998-April 1999

Member of design team working on a single chip MPEG-2 encoder for use in digital camcorders and computers. Implemented the variable length encoding and motion estimation blocks using VHDL and Synopsis tools. The motion estimation used hardware engine capable of doing 32 macroblock comparisons simultaneously. Hardware supported full search and various 2 layer search algorithms.
Worked on DVD player controller embedded processor core and integrated other peripheral IC onto a single circuit.

McDonnell Douglas (Boeing)
Huntington Beach, CA
Information System Division
May 1987-March 1998

Developed architecture for aerial camera for capturing 32K x 32K pictures from multiple-tap line CCD and compressing the data using wavelet compression onto a tape drive. Camera was capable of taking a new picture every 2 seconds. Architecture involved analog front end design for CCD line sensors, CCD noise cancellation circuits, wavelet video compression FPGAs, and system controller board selection. The proposal was accepted by customer and is currently being manufactured.

Demonstrated use of wavelet technology for compressing still pictures in aerial surveillance applications using single FPGA. Designed controller for a megapixel Kodak camera and used 5-3 biorthogonal wavelet transform coupled with run-length with Huffman encoding for compression. Implemented design using Altera 100K FPGA and VHDL. Coordinated software development for demonstration which used VME PowerPC running WindRiver RTOS.

Worked on LASER based mine detection system for Naval Research Lab and Sanders. Developed two FPGAs (Actel and Xilinx) to capture CCD video and control operation of LASER video capture. Wrote real-time software for embedded processor (80186B) to control operation of system. Designed ISA board to provide a test fixture for completed systems and to emulate parts of the system still in development. ISA board used Xilinx gate array. Developed software for ISA board to interface with system and display testing results. Provided technical support for system integrator in designing and debugging high-speed logic. Proposed improved version of LASER video capture that would place two boards of electronics onto a single ASIC.

Designed and implemented fiber optic switch for Space Station. Implemented crossbar switch using AMI 20K ECL gate array. Designed control board to interface with 1553 data bus using three Actel gate arrays.

Designed and implemented embedded controller board that provided data switch functionality through Xilinx FPGA.

Led design team to develop GaAs DSP ASICs for video image processing on a DARPA sponsored program.

Developed architecture for 24-bit DSP and surrounding system by performing tradeoff studies using C++ RTL model. RTL was implemented into a Vitesse 200K gate array using Mentor Graphics schematic capture and Synopsis design compiler. Worked with compiler developers to port gnu C compiler to DSP. GaAs ASIC worked on first pass. Use innovative Built-in Self-Test (BIST) for production testing and produced the highest speed DSP of its time (200 MFLOPS). This program was later expanded to implement the whole video processor system on a thick-film MCM. Modified GaAs DSP to include IEEE 1149.1 boundary scan technology to aid testing of MCM. Worked with MCM manufacturer (IBM) to produce a successful product.

Consulted for Japanese company to develop architecture for 500-MHz superscalar MIPS 4000 compatible processor using custom GaAs ICs. Processor could issue four instruction simultaneously.

Developed fault tolerant computer architecture for space-based application for Air Force using custom CMOS circuits. Worked on proposal and customer demonstrations to win large contract for development of architecture. Performed architecture tradeoffs using RTL model developed in C. Added innovative fault detection and recovery schemes that resulted in three patents being filed by the US Patent Office. Included state of the art testing logic including BIST, JTAG, and design for test (DFT) methodology. Consulted for company (TRW) performing gate level implementation of the design. Product is currently used in several satellite programs.

Rockwell (Boeing)
Anaheim, CA
Aeronautics Division May 1985-May 1987

Part of research and development team developing the next generation of radiation-hardened computers for use in Rockwell strategic missile programs.

Hughes Aircraft (Raytheon)
Fullerton, CA
Display Division June 1978-May 1985

Developed and implemented single board computer using two CMOS ASICs (LSI) and hybrids (Hughes) to control communication terminal. Communication terminal used TDMA and CDMA protocols. Worked with integration partners at ITT Avionics.

Redesigned bit-sliced computer for use in Navy MK-48 torpedo. Took 10 board design and compacted it into 5 boards with doubled performance e. Worked with internal customers to define and develop computer architecture.

Performed upgrades to computers used in Army Fire Finder systems.

Education

California State University
Fullerton, CA
MSEE concentrating in computer architecture

Ohio Northern University
Ada, OH

BSEE

UCLA Extended Education
Westwood, CA

Introduction to Charge Coupled Devices short course

Patents and Papers

The Architecture of a Radiation Hard 32-bit Reduced Instruction Set Computer; GOMAC 1990
A GaAs DSP Based Sided Target Recognition Processor for OH-58D; GOMAC 1993
A 200 MFLOP GaAs Digital Signal Processor; GOMAC 1993
100 MHz Digital Signal Processor MCM; ASEM 1994
200 MFLOP Digital Signal Processor MCM; GOMAC 1997
Signature Monitoring in RISC Patent Pending
Micro-Retry in RISC Patent Pending
Quick-Look Compare Patent Pending

Skills

Hardware modeling and simulation
C, C++, FORTRAN, and various assembly languages
Real-time software programming
Mentor, Modeltech, Synopsis, verilog, VHDL, and other vendor ASIC tools
Actel, Altera, Cypress, and Xilinx FPGA design experience
Experience using CAD on HP, SUN, and PC equipment

Personal

Married for over 20 years with three children
Member of IEEE
Coach and referee soccer games
Leader and organizer of 230 member nonprofit children's club
Top-secret clearance active less than a year ago